1. Field of the Invention
The present invention relates to an asymmetric error correction apparatus and method, and clock recovering apparatus and data recovering apparatus for an optical reading system employing the error correction apparatus. In particular, the present invention relates to an asymmetric error correction apparatus and method, and clock recovering apparatus and data recovering apparatus for an optical reading system employing the same that can correct distortion of a radio frequency (RF) signal caused by interference among data due to inaccurate pit and land lengths during data writing on an optical recording medium. The present application is based on Korean Application No. 2001-48227, filed Aug. 10, 2001, which is incorporated herein by reference.
2. Description of the Related Art
An optical recording system forms a pit corresponding to a signal to be recorded on an optical reading medium such as a compact disc (CD) or digital versatile disc (DVD). However, if data is recorded with an inaccurate pit length during a signal recording process, an asymmetric phenomenon of an RF signal is presented. In case that the pit violates an adjacent data bit region, a positive asymmetry of the signal is presented. In case that the pit is formed in a portion of the necessary data bit region, a negative asymmetry of the signal is presented.
In case that such an asymmetric phenomenon of the RF signal is presented, an inter-symbol interference (ISI) is produced while the optical reading system reads the signal recorded on the optical recording medium. The ISI makes it difficult to detect and correct a frequency error and phase error generated between the recorded data and read data. This causes the reproduced data to be distorted.
Conventionally, in order to solve this problem, a DC offset that is the asymmetric signal is removed using a digital sum value (DSV) asymmetric error correction apparatus applying a DSV algorithm as shown in FIG. 1 or a zero-crossing 3 (ZC3) asymmetric error correction apparatus applying three samples adjacent to a zero-crossing point as shown in FIGS. 2 and 3.
The conventional DSV asymmetric error correction apparatus 1 includes a binary quantization section 1, a counting section 12, a comparing section 13, an error judgment section 14, an integration section 15, a correction section 16, and a data detection section 17.
The binary quantization section 11 determines a polarity value to be “1” if an average value of two samples is larger than “0” for each digital sample, and determines the polarity value to be “−1” if the average value of the two samples is smaller than “0”. The counting section 12 accumulates the detected polarity values to judge the degree of error. The comparing section 13 compares the accumulated polarity value with a predetermined threshold value.
The error judgment section 14 judges that the asymmetric error is generated if the accumulated polarity value exceeds the predetermined threshold value. The integration section 15 accumulates the detected asymmetric errors. The correction section 16 corrects an input signal Si and outputs a corrected signal Sc if the accumulated error value reaches a predetermined value. The data detection section 17 detects respective data bit values of the corrected signal Sc.
The ZC3 asymmetric error correction apparatus 2, which is another correction apparatus for correcting the asymmetric error, will now be explained with reference to FIGS. 2 and 3.
The ZC3 asymmetric error correction apparatus 2 includes a zero-crossing detection section 21, an absolute value comparing section 22, an asymmetric polarity judgement section 23, a counting section 24, a comparing section 25, an error judgment section 26, an integration section 27, a correction section 28, and a data detection section 29.
The zero-crossing detection section 21 detects a zero-crossing point by comparing sign bits of the two samples sequentially inputted. If the zero-crossing point is detected, the absolute value comparing section 22 compares absolute values of the two samples, judges that the asymmetry is generated in the sample having a smaller absolute value, and determines the sample having the smaller absolute value to be an intermediate sample. The asymmetric polarity judgement section 23 judges the polarity value of the signal from the sum of the intermediate sample and two neighboring samples, i.e., one sample at each side of the intermediate sample, thereby using the sum of three samples neighboring the zero-crossing point.
The counting section 24 accumulates the detected polarity value to judge the degree of error. The comparing section 25 compares the accumulated polarity value with the predetermined threshold value. The error judgment section 26 judges that the asymmetric error is generated if the accumulated polarity value exceeds the predetermined threshold value. The integration section 27 accumulates the detected asymmetric error. The correction section 28 corrects the input signal Si by adjusting the gain of the accumulated error value, and outputs the corrected signal Sc. The data detection section 29 detects the respective data bit values of the corrected signal Sc.
The detailed construction and operation of the zero-crossing section 21, absolute value comparing section 22, and asymmetric polarity judgement section 23 are illustrated in FIG. 3
The zero-crossing detection section 21 includes an exclusive OR gate 21a that judges the zero-crossing point from the sign bits of the two sequential samples D2k and D3k. If the zero-crossing point is detected between the two sequential samples D2k and D3k, the zero-crossing detection section 21 sets the detected zero-crossing point value ZC to 1.
The absolute value comparing section 22 obtains absolute values of the two sequential samples D2k and D3k between which the zero-crossing point is detected, and compares the absolute values. The absolute value comparing section 22 judges that the asymmetry is generated in the sample D2k or D3k having a smaller absolute value. For example, if |D2k| is larger than |D3k|, the absolute value comparing section 22 selects D3k as the intermediate sample, and an adder 23a obtains the sum sum—1 of the intermediate sample D3k, previous sample D2k, and later sample D4k. Meanwhile, if |D2k| is smaller than or equal to |D3k|, the absolute value comparing section 22 selects D2k as the intermediate sample, and an adder 23b obtains the sum sum—2 of the intermediate sample D2k, previous sample D1k, and later sample D3k.
A polarity judgment section 23c judges the polarity value to be negative if the detected zero-crossing value ZC is 1, and the sum—n is larger than 0. The polarity judgment section 23c judges the polarity value to be positive if the detected zero-crossing value ZC is 1, and the sum—n is smaller than or equal to 0. Here, n is 1 or 2. The polarity value obtained as above is inputted to the counting section.
The conventional DSV asymmetric error correction apparatus has an advantage that it can achieve a relatively stable operation without being greatly affected by the amount of the asymmetric polarity and the timing error value. However, since the average value of two samples should be obtained for each sample, the conventional apparatus has the disadvantage of slow correction speed as shown in FIG. 12.
Also, the conventional ZC3 asymmetric error correction apparatus, which judges the polarity using the two sample values at the zero-crossing point, can easily judge the polarity in case that the asymmetric polarity is small and the timing error is small as shown in FIG. 13. However, since it uses three samples neighboring the zero-crossing point, it has the disadvantage that it is difficult to accurately judge the polarity of the asymmetric signal in case that the environment of the optical channels is inferior. Accordingly, the amount of jitter in a normal state becomes larger during the error tracking in the correction process as shown in FIGS. 14 and 15, and thus it has the disadvantage that it is difficult to achieve a stable operation of the following PLL loop.